High performance Integrated Circuit (IC) chips are typically very complex with very powerful logic functions. Typical such high performance ICs, commonly include on-chip memory for local storage, e.g., a static random access memory (SRAM) macro. Multi-port SRAMs may be used for pipeline registers, for example. Also, for reliable operation, the typical high performance IC includes some form of Built In Self Test (BIST) as well. Thus, very often an SRAM macro must be designed for multimode operation, capable of transferring data to/from the SRAM macro depending upon the current operating mode, e.g., normal system operation, Array BIST (ABIST) operation, Logic BIST (LBIST) operation and etc. A typical SRAM macro, as with any typical storage, has very critical internal (to the SRAM macro) timing constraints that, if violated, cause array failures. These failures may be very difficult to isolate and identify, whether tested using BIST or otherwise. Typically, to contain, control and thus, minimize this criticality/sensitivity, SRAM macros include locally clocked boundary latches at inputs and outputs, e.g., dual port latches latching read/write addresses for decoding word lines or bit lines and etc. It is important to correctly latch SRAM macro boundary input/output (I/O) states race free, i.e., to correctly latch the current input/output address and to avoid latching/driving portions of addresses from two sequential accesses, e.g., where a read address is presented during a read.
However, circuits designed for multimode operation must interface with adjacent logic differently, depending upon the current operating mode. For example multi-mode circuits must be capable of receiving test patterns with wide timing margins during BIST, and, otherwise, receiving logic signals designed to squeeze every bit of performance out of the particular data path. So, unfortunately, multimode operation exacerbates SRAM design criticality/sensitivity, particularly, in switching between operating modes and because the particular operation mode determines how each (I/O) signal passes to/from the SRAM macro. This all further complicates I/O latch timing, e.g., crucial address arrival times as well as clock arrival times.
Thus, there is a need for SRAM macro clocking logic that maintains intra macro timing regardless of operating mode.